PhD Intern - Machine Learning
Full/Part Time: Part-Time
The High Performance Computing group (HPC) seeks a Ph.D. intern for conducting research in creating a reconfigurable (e.g., FPGA) design and solution for enabling efficient binarized neural network processing. This will be part of HPC exploration in approximated deep learning strategy in coordination with other accelerator solutions. The candidates require hardware FPGA design background as well as knowledge of parallel processing and architecture acceleration. The Ph.D. candidates should also have a good track record in publishing at top-tier HPC or computer architecture conferences.
Equal Employment Opportunity
PNNL is an Equal Opportunity/Affirmative Action Employer that is committed to hiring a diverse, talented workforce. EOE Disability/Vet/M/F/Sexual Orientation/Gender Identity. Staff at PNNL must be able to demonstrate the legal right to work in the United States.
Candidates must be currently enrolled/matriculated in a PhD program at an accredited college. Minimum GPA of 3.0 is required.
The student is expected to have more than 2 years’ experience in FPGA design, deep learning hardware design, computer architecture and parallel programming. Preference will be given to students with strong match background and adequate experiences in FPGA design and deep learning algorithms.
The student should be pursuing PhD in computer science/Electrical Engineering.
Organization and Job ID
Job ID: 307422
Directorate: Physical & Computational Sciences
Division: Advanced Comput, Math & Data
Group: High Performance Computing